Lattice Solutions

Everything you need to quickly and easily complete your design

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  • Embedded Vision Development Kit

    Board

    Embedded Vision Development Kit

    Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
    Embedded Vision Development Kit
  • CrossLink-NX Evaluation Board

    Board

    CrossLink-NX Evaluation Board

    For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
    CrossLink-NX Evaluation Board
  • ECP5 Evaluation Board

    Board

    ECP5 Evaluation Board

    Evaluation and development for ECP5-5G FPGA - 85K LUTs. Includes generous IO access and easy expansion to PMOD, Arduino, RaspberryPI, SERDES interface and more
    ECP5 Evaluation Board
  • Object Counting

    Reference Design

    Object Counting

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting
  • CNN Accelerator IP

    IP Core

    CNN Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Accelerator IP
  • CNN Compact Accelerator IP

    IP Core

    CNN Compact Accelerator IP

    Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
    CNN Compact Accelerator IP
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • CSI-2/DSI D-PHY Receiver

    IP Core

    CSI-2/DSI D-PHY Receiver

    Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Receiver
  • MIPI CSI-2 Virtual Channel Aggregation

    Reference Design

  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Reference Design

  • 4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

    Demo

  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • HM01B0 UPduino Shield

    Board

    HM01B0 UPduino Shield

    A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
    HM01B0 UPduino Shield
  • Human Counting

    Demo

    Human Counting

    Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
    Human Counting
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