Lattice Solutions

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  • Lattice Sentry QSPI Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on SPI/QSPI bus to identify and block potentially illegal traffic.
    Lattice Sentry QSPI Monitor IP Core for MachXO3D
  • Lattice Sentry QSPI Streamer IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Streamer IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Provides fast SPI memory access for firmware authentication as part fo Platform Root of Trust operation
    Lattice Sentry QSPI Streamer IP Core for MachXO3D
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  • SPI Slave IP Core

    IP Core

  • LXO2000

    Board

    LXO2000

    The TEL0001 "LXO2000" is a low cost FPGA module integrating a Lattice XO2-4000 and on-board USB/JTAG. It's compatible to the Arduino MKR standard.
    LXO2000
  • DCA1000 Evaluation Module

    Board

    DCA1000 Evaluation Module

    The DCA1000EVM receives LVDS-format radar-sensing data and can stream over Ethernet in real-time. The board also connects to TI’s 77GHz xWR1xxx EVM.
    DCA1000 Evaluation Module
  • PDM Microphone Aggregation

    Reference Design

    PDM Microphone Aggregation

    Aggregate up to 8 PDM microphones and connection to a processor over I2S or SPI with no impact in audio quality. Ideal for beam-forming. PCM output at 48HKz.
    PDM Microphone Aggregation
  • Infrared Remote Tx/Rx Reference Designs

    Reference Design

    Infrared Remote Tx/Rx Reference Designs

    Implements an interface to IR receive and/or IR transmit. This includes PWM (pulse width modulation) timing and protocol conversion to an SPI /I2C bus
    Infrared Remote Tx/Rx Reference Designs
  • Long Range (LoRa) Wireless

    Reference Design

    Long Range (LoRa) Wireless

    Implement a LoRa compliant device using a tiny iCE40 UltraPlus FPGA, for low-power, low-footprint wireless communication over miles
    Long Range (LoRa) Wireless
  • Graphics Acceleration

    Reference Design

    Graphics Acceleration

    Enables a processor to save power in sleep mode while the low-power iCE40 UltraPlus drives a mobile DSI display, and monitors for wake-up signals.
    Graphics Acceleration
  • Sensor Interfacing and Preprocessing

    Reference Design

    Sensor Interfacing and Preprocessing

    Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
    Sensor Interfacing and Preprocessing
  • SPI Slave to PWM Generation

    Reference Design

    SPI Slave to PWM Generation

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    SPI Slave to PWM Generation
  • SPI-to-UART Expander

    Reference Design

    SPI-to-UART Expander

    Acts as a SPI port expander, multiplexing and demultiplexing read/write data through the SPI slave to multiple UARTs
    SPI-to-UART Expander
  • Barcode Emulation

    Reference Design

    Barcode Emulation

    Enables an ordinary LED to transmit barcode data. The LED is driven such that it transmits pulses that can be read by a checkout scanner.
    Barcode Emulation
  • SPI Controller - WISHBONE Compatible

    Reference Design

    SPI Controller - WISHBONE Compatible

    Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.
    SPI Controller - WISHBONE Compatible
  • SPI Slave Peripheral using Embedded Function Block

    Reference Design

    SPI Slave Peripheral using Embedded Function Block

    Implements intuitive interface between an external SPI master and the XO2 internal registers (user logic) or memory extension in XO2.
    SPI Slave Peripheral using Embedded Function Block
  • SPI to MIPI D-PHY

    Reference Design

    SPI to MIPI D-PHY

    Bridges and decompresses video transmitted over SPI to DSI displays, up to 108Mbps. High speed and low-power modes.
    SPI to MIPI D-PHY
  • SPI Flash Controller with Wear Leveling

    Reference Design

    SPI Flash Controller with Wear Leveling

    Implements the wear leveling control of data storage for SPI Flash memory - stores the number of erases, logic-map-physical table, and the valid page pointers.
    SPI Flash Controller with Wear Leveling
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