Lattice Solutions

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Providers
  • CrossLink-NX VIP Sensor Input Board

    Board

    CrossLink-NX VIP Sensor Input Board

    Intended for use with the Lattice Embedded Vision Development Kit. Includes 4 camera inputs and HyperRam for embedded video applications with CrossLink-NX
    CrossLink-NX VIP Sensor Input Board
  • CrossLink-NX Evaluation Board

    Board

    CrossLink-NX Evaluation Board

    For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
    CrossLink-NX Evaluation Board
  • Object Counting

    Reference Design

    Object Counting

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Byte to Pixel Converter

    IP Core

    Byte to Pixel Converter

    Modular MIPI/D-PHY IP - Converts Parallel Data From a D-PHY Receiver into Pixel Format
    Byte to Pixel Converter
  • CSI-2/DSI D-PHY Receiver

    IP Core

    CSI-2/DSI D-PHY Receiver

    Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Receiver
  • CSI-2/DSI D-PHY Transmitter

    IP Core

    CSI-2/DSI D-PHY Transmitter

    Modular MIPI/D-PHY IP - PHY for transmitting MIPI CSI-2/DSI Data. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Transmitter
  • Pixel to Byte Converter

    IP Core

    Pixel to Byte Converter

    Modular MIPI/D-PHY IP - Converts Pixel Format Data to Parallel Byte Format
    Pixel to Byte Converter
  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • 4 to 1 Image Aggregation with CrossLink-NX

    Reference Design

    4 to 1 Image Aggregation with CrossLink-NX

    Modular MIPI/D-PHY Reference Design - Aggregates four MIPI CSI-2 inputs to a single output stream.
    4 to 1 Image Aggregation with CrossLink-NX
  • MIPI CSI-2 Virtual Channel Aggregation

    Reference Design

    MIPI CSI-2 Virtual Channel Aggregation

    Modular MIPI/D-PHY Reference Design - Adaptable and flexible solution combines multiple MIPI CSI-2 inputs to a single CSI-2 output stream.
    MIPI CSI-2 Virtual Channel Aggregation
  • 4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

    Demo

    4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

    Modular MIPI/D-PHY Demonstration - Aggregates four MIPI CSI-2 inputs to a single parallel output stream, which is then displayed on HDMI.
    4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo
  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • Human Counting

    Demo

    Human Counting

    Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
    Human Counting
  • Tri-Speed Ethernet MAC Core IP

    IP Core

    Tri-Speed Ethernet MAC Core IP

    Transmits and receives data between a host processor and an Ethernet network. IEEE 802.3 compliant. Supports 10/100/1000 operation.
    Tri-Speed Ethernet MAC Core IP
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  • SPI Slave IP Core

    IP Core

    SPI Slave IP Core

    Interfaces to SPI bus. Configurable data width, polarity, clocking modes and memory interface.
    SPI Slave IP Core
  •  I2C Slave IP Core

    IP Core

    I2C Slave IP Core

    Interfaces to an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
     I2C Slave IP Core
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