Lattice Solutions

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  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • Universal Asynchronous Receiver/Transmitter

    Reference Design

    Universal Asynchronous Receiver/Transmitter

    Fully configurable UART functionally compatible with the NS16450 UART
    Universal Asynchronous Receiver/Transmitter
  • I2C Slave/Peripheral

    Reference Design

    I2C Slave/Peripheral

    Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment
    I2C 
    I2C Slave/Peripheral
  • I2C Slave to SPI Master Bridge

    Reference Design

    I2C Slave to SPI Master Bridge

    Implements an I2C slave to SPI master bridge.
    I2C, SPI 
    I2C Slave to SPI Master Bridge
  • BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    Reference Design

    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    A multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface
    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)
  • Power Management Bus

    Reference Design

    Power Management Bus

    Implements the Data Link Layer protocol of the Power Management Bus, conneting to a WISHBONE interface
    Power Management Bus
  • Long Delay Timer Functions

    Reference Design

    Long Delay Timer Functions

    Demontrates the techniques necessary for generating long duration timeouts. Timeouts of 2, 4 8 or 16 seconds are demonstrated
     
    Long Delay Timer Functions
  • Platform Manager Utility Function Core IP

    IP Core

    Platform Manager Utility Function Core IP

    Supports Fault Logging and Enhanced Closed-loop Trim power management functions.
    Platform Manager Utility Function Core IP
  • SPI GPIO Expander

    Reference Design

    SPI GPIO Expander

    Expand microprocessor general purpose I/O ports with a Serial Peripheral Interface (SPI)
    SPI GPIO Expander
  • GPIO Expander

    Reference Design

    GPIO Expander

    Provides a solution that uses a Lattice PLD as a GPIO Expander
    GPIO Expander
  • Circuit Board Fault Monitoring and Logging

    Reference Design

    Circuit Board Fault Monitoring and Logging

    Records the supply fault condition in non-volatile memory so the fault(s) can read back at a later time
    Circuit Board Fault Monitoring and Logging
  • Closed Loop Power Supply Trimming

    Reference Design

    Closed Loop Power Supply Trimming

    Monitor and control different power supplies. Improve supply precision to <1.0% output error. Set pre-determined output levels.
     
    Closed Loop Power Supply Trimming
  • SPI Peripheral

    Reference Design

    SPI Peripheral

    Implements a Serial Peripheral Interface (SPI) slave device interface that provides full-duplex, synchronous, serial communication with a SPI master
    SPI Peripheral
  • ADC Temperature Measurement Readout

    Reference Design

    ADC Temperature Measurement Readout

    Demonstrates the input of ambient temperature using an input voltage developed using an external resistor/thermistor and interface to the on-chip ADC using I2C
    ADC Temperature Measurement Readout
  • Platform Manager Development Kit

    Board

    Platform Manager Development Kit

    No longer available - for reference only. For evaluation & development with the Platform Manager ( LPTM10-12107 - 208-ball ftBGA) + 35mm slide pots.
    Platform Manager Development Kit
  • ProcessorPM Development Kit

    Board

    ProcessorPM Development Kit

    No longer available - for reference only. Low-cost platform for evaluating and designing with the ProcessorPM (605 and 6AT6) power management device.
    ProcessorPM Development Kit
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