Lattice Solutions

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Providers
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • Universal Asynchronous Receiver/Transmitter

    Reference Design

    Universal Asynchronous Receiver/Transmitter

    Fully configurable UART functionally compatible with the NS16450 UART
    Universal Asynchronous Receiver/Transmitter
  • SDR SDRAM Controller - Advanced

    Reference Design

    SDR SDRAM Controller - Advanced

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller - Advanced
  • ispMACH 4256ZE Breakout Board

    Board

    ispMACH 4256ZE Breakout Board

    A simple low-cost board that provides complete I/O access to the ispMACH4256ZE (TN144 package)+LEDs, Prototyping area and more.
    ispMACH 4256ZE Breakout Board
  • BSCAN - Multiple Port Linker (BSCAN2)

    Reference Design

    BSCAN - Multiple Port Linker (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    BSCAN - Multiple Port Linker (BSCAN2)
  • I2C Bus Controller for Serial EEPROMs

    Reference Design

    I2C Bus Controller for Serial EEPROMs

    Provides an interface between standard microprocessors and I2C Serial EEPROM devices
    I2C Bus Controller for Serial EEPROMs
  • I2C Slave/Peripheral

    Reference Design

    I2C Slave/Peripheral

    Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment
    I2C 
    I2C Slave/Peripheral
  • SPI Controller - WISHBONE Compatible

    Reference Design

    SPI Controller - WISHBONE Compatible

    Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.
    SPI Controller - WISHBONE Compatible
  • LPC (Low Pin Count) Bus Controller

    Reference Design

    LPC (Low Pin Count) Bus Controller

    Implements a Low Pin Count bus controller - based on the Intel Low Pin Count Interface Specification (version 1.1)
    LPC (Low Pin Count) Bus Controller
  • Read and Write Usercode

    Reference Design

    Read and Write Usercode

    Read or change a Usercode or User Electronic Signature (UES) through general I/O without reprogramming the entire on-device Flash or interrupting the system.
    Read and Write Usercode
  • BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    Reference Design

    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    A multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface
    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)
  • PCI Target 32-bit/33MHz

    Reference Design

    PCI Target 32-bit/33MHz

    Fully Compliant with PCI 2.2 specification.
    PCI Target 32-bit/33MHz
  • SPI GPIO Expander

    Reference Design

    SPI GPIO Expander

    Expand microprocessor general purpose I/O ports with a Serial Peripheral Interface (SPI)
    SPI GPIO Expander
  • GPIO Expander

    Reference Design

    GPIO Expander

    Provides a solution that uses a Lattice PLD as a GPIO Expander
    GPIO Expander
  • HDLC Controller

    Reference Design

    HDLC Controller

    Implements HDLC (High-Level Data Link Control), located at the OSI link layer 2. supports LAPB, LAPD, LLC and SDLC with a few modifications
    HDLC Controller
  • PWM Fan Controller - WISHBONE Compatible

    Reference Design

    PWM Fan Controller - WISHBONE Compatible

    Implements a PWM fan control using a PLD and a MOSFET circuit to provide the speed control of a simple 2-pin or 3-pin fan.
    PWM Fan Controller - WISHBONE Compatible
  • SPI Peripheral

    Reference Design

    SPI Peripheral

    Implements a Serial Peripheral Interface (SPI) slave device interface that provides full-duplex, synchronous, serial communication with a SPI master
    SPI Peripheral
  • Wake on LAN

    Reference Design

    Wake on LAN

    WoL allows a load/client on a network to be turned on by a message sent via the network, saving power by keeping the device in stand-by mode until needed.
    Wake on LAN
  • Fast Page Mode DRAM Controller

    Reference Design

    Fast Page Mode DRAM Controller

    Implements a Fast Page Mode (FPM) DRAM Controller
    Fast Page Mode DRAM Controller
  • Standard SDRAM Controller for ispMACH Devices

    Reference Design

    Standard SDRAM Controller for ispMACH Devices

    SDRAM Interface to standard microprocessors, independent of the processor type. The design as shown supports two 16MB memory regions configured as 4 M x 32 bits
    Standard SDRAM Controller for ispMACH Devices
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