7:1 LVDS Video Interface

Reference Design LogoSource synchronous interfaces consisting of multiple data bits and clocks have become a common method for moving image data within electronic systems. A prevalent standard is the 7:1 LVDS interface (employed in Channel Link, Flat Link, and Camera Link), which has become a common standard in many electronic products including consumer devices, industrial control, medical, and automotive telematics. Lattice's 7:1 LVDS Video Interface Reference Design has been optimized for use with the LatticeECP3, LatticeECP2/M, and LatticeXP2 FPGA families. The reference design implements standard 7:1 LVDS interfaces using the FPGA I/O structure. Transmit and receive interfaces are fully and efficiently implemented by specifically taking advantage of dedicated LVDS I/O, the generic DDR I/O interface, gearing, and PLL clocking of edge and system clocks. Data formatting is also accomplished using dedicated deserializer modules.

Lattice 7:1 LVDS Video Demo Kit

The Lattice 7:1 LVDS Video Demo Kit is a set of boards and cables that demonstrate the implementation of a 7:1 LVDS solution using the LatticeECP2 or LatticeXP2 FPGA. The kit works with the LatticeECP2 or LatticeXP2 Advanced evaluation boards, as well as various user video I/O resources.

Block Diagram

Performance and Size

Design 1: Results for Loopback Test
Date Family Language SLICEs LUTs Registers sysMEM EBRs sysDSP™ Blocks fMAX(MHz)
Apr 2011 ECP3-95 VHDL 771 832 (1%) 910 0 (0%) 0 (0%) 108
Apr 2011 ECP3-95 Verilog 766 819 (1%) 916 0 (0%) 0 (0%) 108
Apr 2011 ECP2/M-50 VHDL 794 858 (2%) 914 0 (0%) 0 (0%) 108
Apr 2011 ECP2/M-50 Verilog 778 834 (2%) 916 0 (0%) 0 (0%) 108
Apr 2011 XP2-17 VHDL 785 839 (5%) 916 0 (0%) 0 (0%) 108
Apr 2011 XP2-17 Verilog 774 825 (5%) 915 0 (0%) 0 (0%) 108

Performance and utilization characteristics are generated using Lattice ispLEVER® 7.0 SP1 software for LatticeECP2/M and LatticeXP2 devices, and ispLEVER7.2 SP2 software for LatticeECP3 devices. When using this IP core in a different density, speed, or grade within the LatticeECP2/M, LatticeXP2 and LatticeECP3 families, performance and utilization may vary.

Design 2: Results for Video_Demo Test
Date Family Language SLICEs LUTs Registers sysMEM EBRs sysDSP™ Blocks fMAX(MHz)
Apr 2011 ECP3-95 VHDL 1420 1848 (2%) 1347 10 (4%) 4.125 (12%) 108
Apr 2011 ECP3-95 Verilog 1415 1852 (2%) 1315 10 (4%) 4.125 (12%) 108
Apr 2011 ECP2/M-50 VHDL 1428 1804 (4%) 1293 8 (38%) 4.125 (23%) 108
Apr 2011 ECP2/M-50 Verilog 1433 1857 (4%) 1253 10 (48%) 4.125 (23%) 108
Apr 2011 XP2-17 VHDL 1492 1803 (11%) 1292 8 (53%) 4.125 (82%) 108
Apr 2011 XP2-17 Verilog 1482 1848 (11%) 1254 10 (67%) 4.125 (82%) 108

Note: Performance and utilization characteristics are generated using Lattice ispLEVER 7.0 SP1 software for LatticeXP2 and LatticeECP2/M devices, and ispLEVER 7.2 SP2 software for LatticeECP3 devices. When using this IP core in a different density, speed, or grade within the LatticeECP2/M, LatticeXP2 and LatticeECP3 families, performance and utilization may vary.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP3, LatticeECP2/M, LatticeXP2 7:1 LVDS Video Interface Reference Design
RD1030 1.5 4/12/2011 PDF 750.1 KB
LatticeECP3, LatticeECP2/M, LatticeXP2 7:1 LVDS Video Interface Reference Design Files
Contains Verilog and VHDL source files for RD1030 and use with the 7:1 LVDS Video Demo hardware from Lattice.
RD1030 1.5 4/12/2011 ZIP 1.8 MB