SPI to MIPI D-PHY

Flexible MIPI (Mobile Industry Processor Interface) DSI (Display Serial Interface) Tx Bridge for iCE40 UltraPlus. This bridge provides the ability to capture real time video, buffer and at the same time display it at very low power.

SPI to MIPI D-PHY

Features

  • Supports one data lane up to 108 Mbps
  • Supports high speed and low power modes
  • Supports DSI, RGB, YCbCr and User Defined formats
  • Compressed images sent through the SPI input port and stored in the integrated SRAM
  • Images are decompressed within iCE40 UltraPlus before being driven over the MIPI DSI interface

Block Diagram

Buffer Demo

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 UltraPlus Display Frame Buffer Demo
1.0 4/13/2017 ZIP 87.4 MB
iCE40 UltraPlus Display Frame Buffer Demo User Guide
FPGA-UG-02009 1.1 4/13/2017 PDF 809 KB
iCE40 UltraPlus Display Frame Buffer with BLE Source Files
1.0 4/13/2017 ZIP 11.1 MB