MIPI DSI Receive Bridge

DSI Receive Reference Design

Flexible MIPI (Mobile Industry Processor Interface) DSI (Display Serial Interface) Receive Bridge - Allows an AP (Application Processors) to interface to a screen that is not designed for mobile applications.

MIPI DSI RX Diagram

Features

  • Supports up to 4 data lanes at up to ~ 900 Mbps per lane
  • HS (High Speed) Mode receive
  • LP (Low Power) Mode transmit and receive
  • Typical power for 2 data lane bridge running at 700 Mbps is 20 mW
  • Typical power for 4 data lane bridge running at 700 Mbps is 32 mW
  • Provides a DCS (Display Command Set) encoder for display controls
  • Supports DSI formats RGB, YCbCr and User Defined
  • Output parallel RGB bus supporting up to 36 bits with clock, Hsync & Vsync

Jump to

Block Diagram

Documentation

Quick Reference
Technical Resources
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI D-PHY Bandwidth Matrix Table User Guide
FPGA-UG-02041 1.1 5/15/2018 PDF 1011.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI DPHY DSI/CSI-2 Example Schematic
1.0 10/29/2013 PDF 72.6 KB
MIPI D-PHY Bandwidth Matrix Table User Guide
FPGA-UG-02041 1.1 5/15/2018 PDF 1011.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
DSI Rx Reference Design - Documentation
RD1185 1.3 4/1/2014 PDF 2.1 MB
DSI Rx Reference Design - Source Code
RD1185 1.4 1/1/2015 ZIP 1.6 MB
LatticeECP3 RGB101010 1L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
LatticeECP3 RGB666 1L
RD1185 2.0 8/18/2015 ZIP 1 MB
LatticeECP3 RGB666 2L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
LatticeECP3 RGB666 4L
RD1185 2.0 8/18/2015 ZIP 1.3 MB
LatticeECP3 RGB888 1L
RD1185 2.0 8/18/2015 ZIP 1 MB
LatticeECP3 RGB888 2L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
LatticeECP3 RGB888 4L
RD1185 2.0 8/18/2015 ZIP 1.2 MB
LatticeECP3 YCbCr422 4L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
MachXO2 RGB565 1L
RD1185 2.0 8/18/2015 ZIP 993.3 KB
MachXO2 RGB565 2L
RD1185 2.0 8/18/2015 ZIP 1 MB
MachXO2 RGB565 4L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
MachXO2 RGB666 1L
RD1185 2.0 8/18/2015 ZIP 1013.4 KB
MachXO2 RGB666 2L
RD1185 2.0 8/18/2015 ZIP 1 MB
MachXO2 RGB666 4L
RD1185 2.0 8/18/2015 ZIP 1.2 MB
MachXO2 RGB888 1L
RD1185 2.0 8/18/2015 ZIP 1003.6 KB
MachXO2 RGB888 2L
RD1185 2.0 8/18/2015 ZIP 1 MB
MachXO2 RGB888 4L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
MachXO2 YCbCr420 4L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
MachXO2 YCbCr422 24b 4L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
MachXO3 RGB565 1L
RD1185 2.0 8/18/2015 ZIP 994.8 KB
MachXO3 RGB565 2L
RD1185 2.0 8/18/2015 ZIP 1 MB
MachXO3 RGB565 4L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
MachXO3 RGB666 1L
RD1185 2.0 8/18/2015 ZIP 1014 KB
MachXO3 RGB666 2L
RD1185 2.0 8/18/2015 ZIP 1 MB
MachXO3 RGB666 4L
RD1185 2.0 8/18/2015 ZIP 1.2 MB
MachXO3 RGB888 1L
RD1185 2.0 8/18/2015 ZIP 1003.6 KB
MachXO3 RGB888 2L
RD1185 2.0 8/18/2015 ZIP 1 MB
MachXO3 RGB888 4L
RD1185 2.0 8/18/2015 ZIP 1.1 MB
MachXO3 YCbCr 20b 4L
RD1185 2.0 8/18/2015 ZIP 1.2 MB
MIPI D-PHY Interface IP - Documentation
FPGA-RD-02040 1.6 5/15/2018 PDF 3 MB
MIPI D-PHY Interface IP - Source Code
RD1182 1.5 1/31/2015 ZIP 4.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
MIPI Display Serial Interface Solution Product Flyer
I0241 2.0 10/22/2013 PDF 1.8 MB


If you need a MIPI configuration which doesn't appear as a reference design on this page, contact your local Lattice Sales Office.

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