Deinterlacer

LatticeCoreThe Deinterlacer IP core converts input video stream from interlaced format into progressive format and uses bob, intra and inter motion adaptive deinterlacing algorithms to reduce interline flicker and jagged edge. The Deinterlacer IP core supports YCbCr4:2:2, YCbCr4:4:4 and RGB format, serial and parallel deinterlacing. The Deinterlacer IP core provides a parameter bus for dynamic parameters updating and the parameter bus can be configured running at a separate clock. Also it supports a simple frame rate conversion function.

Interlaced video frames consists of two sequent fields, which are scanned at even and odd lines of the image sensor. Interlaced video has less transmission bandwidth, but most modern displays support progressive frame only. The two interlaced fields must be converted to one progressive frame for display, which is known as deinterlacing. As the two interlaced fields are taken at different time, there will be flicker and jagged edges in the combined frame. A good deinterlacing algorithm should reduce these artifacts as much as possible and provide good video quality in the process. Lattice Deinterlacer IP core provides several deinterlacing algorithms for different video quality and resource: weave, bob, intra and inter motion adaptive deinterlacing algorithms.

Features

  • Supports for single color, YCbCr4:2:2, YcbCr4:4:4 and RGB video formats.
  • Supports serial and parallel deinterlacing.
  • Supports weave, bob, intra and inter motion adaptive deinterlacing algorithms.
  • Supports frame rate conversion.
  • Configurable initial field.
  • Configurable thresholds for inter motion adaptive deinterlacing algorithm.
  • Dynamic parameters updating: frame size, initial field and bypass mode.
  • Configurable parameter bus width.
  • Configurable separate parameters bus clock.
  • Configurable memory bus width and base address.
  • Configurable burst length and burst count.
  • Configurable internal FIFO type and depth.
  • Configurable pixel data width.
  • Configurable line buffer type.

Block Diagram

Performance and Size

LatticeECP21 and LatticeECP2S1
Video Format Frame Width Frame Height Deinterlacer Algorithm Registers LUT4s EBRs fMAX
(iclk)
fMAX
(mem_clk)
fMAX
(oclk)
YCbCr4:2:2 720 576 intra 2612 3144 4 254 278 258
YCbCr4:2:2 720 576 inter 3825 4702 7 294 260 256
YCbCr4:2:2 1920 1080 intra 2657 3223 6 248 262 250
YCbCr4:2:2 1920 1080 inter 3916 4774 11 267 244 242

1. Performance and utilization data are generated targeting a LFE2-50E-7F484C device using Lattice Diamond 1.3 and Synplify Pro E-2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family.

LatticeECPM1 and LatticeECP2MS1
Video Format Frame Width Frame Height Deinterlacer Algorithm Registers LUT4s EBRs fMAX
(iclk)
fMAX
(mem_clk)
fMAX
(oclk)
YCbCr4:2:2 720 576 intra 2612 3144 4 253 291 258
YCbCr4:2:2 720 576 inter 3825 4702 7 296 237 256
YCbCr4:2:2 1920 1080 intra 2657 3223 6 287 275 250
YCbCr4:2:2 1920 1080 inter 3916 4774 11 280 23 242

1. Performance and utilization data are generated targeting a LFE2M50E-7F484C device using Lattice Diamond 1.3 and Synplify Pro E-2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.

LatticeECP31
Video Format Frame Width Frame Height Deinterlacer Algorithm Registers LUT4s EBRs fMAX
(iclk)
fMAX
(mem_clk)
fMAX
(oclk)
YCbCr4:2:2 720 576 intra 2609 3127 4 281 257 249
YCbCr4:2:2 720 576 inter 3833 4690 7 288 245 251
YCbCr4:2:2 1920 1080 intra 2656 3167 6 252 252 244
YCbCr4:2:2 1920 1080 inter 3916 4734 11 243 255 243

1. Performance and utilization data are generated targeting a LFE2-70EA-8FN1156C device using Lattice Diamond 1.3 and Synplify Pro E-2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeXP21
Video Format Frame Width Frame Height Deinterlacer Algorithm Registers LUT4s EBRs fMAX
(iclk)
fMAX
(mem_clk)
fMAX
(oclk)
YCbCr4:2:2 720 576 intra 2612 3144 4 232 247 214
YCbCr4:2:2 720 576 inter 3825 4702 7 228 212 225
YCbCr4:2:2 1920 1080 intra 2657 3223 6 239 233 217
YCbCr4:2:2 1920 1080 inter 3916 4774 11 252 226 221

1. Performance and utilization data are generated targeting a LFXP2-40E-7F484C device using Lattice Diamond 1.3 and Synplify Pro E-2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.

Ordering Information

Family Part Number
LatticeECP3 DLACE-E3-U1
LatticeECP2/S DLACE-P2-U1
LatticeECP2M/S DLACE-PM-U1
LatticeXP2 DLACE-X2-U1

IP Version: 1.0.

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Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Deinterlacer IP Core User's Guide
IPUG97 1.1 9/24/2013 PDF 2.2 MB