Tri-Speed Ethernet MAC Core IP

IP ExpressThe Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbits/sec data rate) or the Fast Ethernet mode (10/100 Mbits/sec data rate). Operation in either Gigabit mode or Fast Ethernet mode is selected by setting an internal register bit.

The Tri-Speed Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through the FIFO interface.

The data received from the G/MII interface is first buffered until sufficient data is available to be processed by the Receive MAC (Rx MAC). The Preamble and the Start of Frame Delimiter (SFD) information are then extracted from the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the received packet and validates whether the frame can be received before transferring it into the FIFO. Only valid frames are transferred into the FIFO. This feature has the following two benefits: the systems need not re-calculate the Frame Check Sequence (FCS) again when the frame is being transmitted, and it also keeps the receive MAC relatively simple. The Tri-Speed MAC, however, always calculates CRC to check whether the frame was received error-free.

On the transmit side, the Tx MAC is responsible for controlling access to the physical medium. The Tx MAC reads data from an external client Tx FIFO, formats this data into an Ethernet packet and passes it to the G/MII module. The Tx MAC reads data from the Tx Client FIFO when the client indicates a packet is available, and the Tx MAC is in its appropriate state. The Tx MAC pre-fixes the Preamble and the Start-of-Frame Delimiter information to the data and appends the Frame Check Sequence at the end of the data. In half-duplex operation, the Tx MAC stores the first 64 bytes of data from the external FIFO in an internal buffer, to be used in re-transmitting data on collisions. The SGMII Easy Connect configuration option adds pins and logic for seamless connection to the Lattice's Gigabit Ethernet PCS IP core.

Features

  • Compliant to IEEE 802.3z standard
  • Generic 8-bit host interface
  • 8-bit wide internal data path
  • Generic transmit and receive FIFO interface
  • Full-duplex operation in 1G mode
  • Full- and half-duplex operation in 10/100 mode
  • Transmit and receive statistics vector
  • Programmable Inter-Packet Gap (IPG)
  • Multicast address filtering
  • Selectable MAC operating options
    • Classic Tri-Speed MAC with G/MII
    • Gigabit MAC with GMII
    • SGMII Easy Connect MAC with GMII, configurable option available on LatticeECP3™, LatticeECP2/M, and LatticeSC/M devices
  • Supports
    • Full-duplex control using PAUSE frames
    • VLAN tagged frames
    • Automatic re-transmission on collision
    • Automatic padding of short frames
    • Multicast and Broadcast frames
    • Optional FCS transmission and reception
    • Optional MII management interface module
    • Jumbo frames up to 9600 bytes

The Tri-Speed Ethernet MAC is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that the FPGA programming bitstream will have time-out logic unless a license for the IP is purchased.

Block Diagram

Performance and Size

ECP5 (LFE5U)1
Configuration SLICEs LUTs REGs EBRs External
Pins
fMAX (MHz)
MIIM Module Operation Mode
No Classic 1245 1694 1193 2 25 125
No Gigabit 1080 1430 1061 1 22 125
No SGMII 1249 1696 1173 2 4 125
Yes Classic 1408 1849 1345 2 27 125
Yes Gigabit 1263 1582 1213 1 24 125
Yes SGMII 1423 1857 1325 2 6 125

1. Performance and utilization data are generated targeting an LFE5U-85F-8BG756C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the Sapphire family.

ECP5 (LFE5UM)1
Configuration SLICEs LUTs REGs EBRs External
Pins
fMAX (MHz)
MIIM Module Operation Mode2
No Classic 1245 1694 1193 2 25 125
No Gigabit 1080 1430 1061 1 22 125
No SGMII 1249 1696 1173 2 4 125
Yes Classic 1408 1849 1345 2 27 125
Yes Gigabit 1263 1582 1213 1 24 125
Yes SGMII 1423 1857 1325 2 6 125

1. Performance and utilization data are generated targeting an LFE5UM-85F-8BG756C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the Sapphire family.

LatticeECP31
Configuration SLICEs LUTs REGs EBRs External
Pins
fMAX (MHz)
MIIM Module Operation Mode
No Classic 1232 1721 1193 2 25 125
No Gigabit 1037 1427 1061 1 22 125
No SGMII 1227 1718 1173 2 4 125
Yes Classic 1355 1872 1345 2 27 125
Yes Gigabit 1186 1596 1213 1 24 125
Yes SGMII 1371 1881 1325 2 6 125

1. Performance and utilization data are generated targeting an LFE3-95EA-8FN484C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeXP21
Configuration SLICEs LUTs REGs EBRs External
Pins
fMAX (MHz)
MIIM Module Operation Mode2
No Classic 1337 1855 1197 2 25 125
No GbE 1086 1450 1061 1 22 125
Yes Classic 1494 3031 1352 2 27 125
Yes GbE 1243 1620 1213 1 24 125

1. Performance and utilization data are generated targeting an LFXP2-17E-6F484C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.
2. The SGMII Easy Connect option is only available on device families with SERDES I/O.

Ordering Information

Part Number
ECP5 TS-MAC-E5-U/TS-MAC-E5-UT
LatticeECP3 TS-MAC-E3-U4
LatticeXP2 TS-MAC-X2-U4

IP Version: 3.3.

Evaluate: To download a full evaluation version of this IP, please go to the Lattice IP Server tab in the IPexpress Main Window. All LatticeCORE IP modules available for download are visible on this tab.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeMico32 Tri-Speed Ethernet MAC Gigabit Demo for the LatticeECP3 Versa Evaluation Board User's Guide
UG47 01.0 4/15/2011 PDF 2.1 MB
Tri-Speed Ethernet MAC User's Guide
IPUG51 3.3 4/4/2015 PDF 5.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP3 Versa - TSMAC Demo - Design Files for Windows
1.0 5/22/2013 EXE 5.8 MB
Tri-Speed Ethernet MAC Demo
8/6/2006 ZIP 5.5 MB