FFT Compiler

IP ExpressLattice's FFT Compiler offers forward and inverse Fast Fourier Transforms for point sizes from 64 to 16384. This IP core can be configured to perform forward FFT, inverse FFT (IFFT) or port selectable forward/inverse FFT. The FFT compiler offers two choices of implementation: high performance (Streaming I/O) and low resource (Burst I/O). In the high performance implementation, the FFT IP core can perform real-time computations with continuous data streaming in and out at clock rate. There can also be arbitrary gaps between data blocks allowing discontinuous data blocks. The low resource implementation can be used when it is required to use lesser slices (logic unit of Lattice FPGA devices) and EBR (Embedded Block RAM) resources or if the device is too small to accommodate the high performance version.

To account for the data growth in fine register length implementations, the FFT compiler allows one of three fixed scaling or dynamic scaling after each radix-2 stage of the FFT computation. The low resource version also supports block floating point arithmetic that provides increased dynamic range for intermediate computations. The FFT compiler also allows the number of FFT points to be varied dynamically through a port.

Features

  • Wide range of points sizes: 64, 128, 256, 512, 1024, 2048, 4096, 8192, and 16384
  • Choice of high-performance (streaming I/O) and low resource (burst I/O) versions
  • Run-time variable FFT point size
  • Forward, inverse or port-configurable forward/inverse transform modes
  • Choice of no scaling, fixed scaling (RS111/RS211) and dynamically variable stage-wise scaling
  • Data precision of 8 to 24 bits
  • Twiddle factor precision of 8 to 24 bits
  • Natural order for input and choice of bit-reversed or natural order for output
  • Support for arbitrary gaps between input data blocks in high-performance realization
  • Block floating point scaling support in low resource configurations

Jump to

Block Diagram

Performance and Size

ECP51
# Points Operating
mode
SLICEs LUTs Registers sysMEM
EBRs
sysDSP
Blocks
fMAX(MHz)
64 Low Resource 583 773 775 3 1 260
64 High Performance 1043 1671 1218 1 2 279
256 Low Resource 605 807 803 3 1 249
256 High Performance 1471 2335 1679 3 3 286
1024 Low Resource 648 882 833 3 1 244
1024 High Performance 1837 2917 2098 6 4 271

1. Performance and utilization data are generated targeting an LFE5UM-85F-8BG756C device using Lattice Diamond 3.10 and Synplify Pro M-2017.03L-SP1-1. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.

LatticeECP31
# Points Operating
mode
SLICEs LUTs Registers sysMEM
EBRs
sysDSP
Blocks
fMAX(MHz)
64 Low Resource 493 668 727 3 2 285
64 High Performance 733 1433 1174 1 2 243
256 Low Resource 575 821 783 3 2 255
256 High Performance 1065 2074 1636 3 3 266
1024 Low Resource 653 964 820 3 2 254
1024 High Performance 1329 2602 2056 6 4 261
8192 Low Resource 722 1089 870 18 2 258
8192 High Performance 1957 3843 2762 21 6 229

1. Performance and utilization data are generated targeting a LFE3-95E-8FN672CES device using Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeECP2M1
# Points Operating
mode
SLICEs LUTs Registers sysMEM
EBRs
sysDSP
Blocks
fMAX(MHz)
64 Low Resource 534 681 730 3 1 286
64 High Performance 989 1437 1174 1 2 243
256 Low Resource 616 830 789 3 1 292
256 High Performance 1419 2070 1636 3 3 266
1024 Low Resource 718 991 839 3 1 273
1024 High Performance 1782 2618 2056 6 4 261
8192 Low Resource 787 1123 897 18 1 234
8192 High Performance 2518 3867 2762 21 6 229

1. Performance and utilization data are generated targeting a LFE2M-35E-7F672C device using Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.

LatticeECP21
# Points Operating
mode
SLICEs LUTs Registers sysMEM
EBRs
sysDSP
Blocks
fMAX(MHz)
64 Low Resource 499 608 695 3 1 283
64 High Performance 723 1435 1174 1 2 283
256 Low Resource 578 745 755 3 1 250
256 High Performance 1049 2078 1636 3 3 250
1024 Low Resource 666 894 804 3 1 258
1024 High Performance 1324 2626 2056 6 4 258
8192 Low Resource 787 1123 897 18 1 240
8192 High Performance 1952 3880 2762 21 6 240

1. Performance and utilization data are generated targeting a LFE2-50-7F672C device using Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family.

LatticeECP/EC1
# Points Operating
mode
SLICEs LUTs Registers sysMEM
EBRs
sysDSP
Blocks
fMAX(MHz)
64 Low Resource 488 588 705 3 1 213
64 High Performance 998 1444 1174 1 2 208
256 Low Resource 575 732 772 3 1 212
256 High Performance 1424 2060 1636 3 3 200
1024 Low Resource 702 957 861 5 1 192
1024 High Performance 1781 2589 2056 7 4 182
8192 Low Resource 769 1055 913 36 1 189
8192 High Performance 2579 3950 2762 38 6 179

1. Performance and utilization data are generated targeting a LFECP33E-5F672C device using Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP family.

LatticeXP21
# Points Operating
mode
SLICEs LUTs Registers sysMEM
EBRs
sysDSP
Blocks
fMAX(MHz)
64 Low Resource 534 681 730 3 1 261
64 High Performance 989 1437 1174 1 2 243
256 Low Resource 616 830 789 3 1 226
256 High Performance 1419 2070 1636 3 3 266
1024 Low Resource 718 991 839 3 1 237
1024 High Performance 1782 2618 2056 6 4 261

1. Performance and utilization data are generated targeting a LFXP2-17E-7F484C device using Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.

Ordering Information

Family Part Numbers Description
ECP5 FFT-COMP-E5-U Single-Design License
ECP5 FFT-COMP-E5-UT Multi-Site License
LatticeECP3 FFT-COMP-E3-U2 Single-Design License
LatticeECP3 FFT-COMP-E3-UT2 Multi-Site License
LatticeECP2M FFT-COMP-PM-U2 Single-Design License
LatticeECP2M FFT-COMP-PM-UT2 Multi-Site License
LatticeECP2 FFT-COMP-P2-U2 Single-Design License
LatticeECP2 FFT-COMP-P2-UT2 Multi-Site License
LatticeEC/ECP FFT-COMP-E2-U2 Single-Design License
LatticeEC/ECP FFT-COMP-E2-UT2 Multi-Site License
LatticeXP2 FFT-COMP-X2-U2 Single-Design License
LatticeXP2 FFT-COMP-X2-UT2 Multi-Site License

IP Version: 2.6.

Evaluate: To download a full evaluation version of this IP for ECP5 devices, go to the Clarity Designer tool and click the Lattice IP Server tab in the window. For all other devices, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP modules available for download are visible in the IP Server window. Please note that the evaluation bitstream generated will have timeout logic present unless a license for the IP is purchased. Timeout logic allows the IP to run on hardware for a limited time (approximately four hours) without requiring an IP license.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice distributor or sales representative.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
FFT Compiler IP Core User Guide
FPGA-IPUG-02045 2.0 7/12/2018 PDF 1.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB


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