CrossLink-NX: Embedded Vision and Processing FPGA

MIPI bridging and Edge AI Combined

Built on the Lattice Nexus Platform - Up to 75% lower power vs similar FPGAs and small form factor packaging with sizes as small as 4 mm x 4 mm.

Provides Best-in-class Performance for Vision Processing Applications - High memory to logic cell ratio, up to 170 bits per logic cell, accelerates AI inferencing.

High Speed Interfaces - 2.5 Gbps Hardened MIPI D-PHY, 5 Gbps PCIe, 1.5 Gbps programmable IO, 1066 Mbps DDR3. Supporting LVDS, subLVDS, OpenLDI (OLDI), SGMII, and FPGA fabric for signal aggregation, duplication, and splitting.

Features

  • Instant-on configuration – IO configures in 3 ms, and device as fast as 8 ms
  • FD-SOI programmable back bias enables per device performance / power optimization
  • Two hardened 4-lane MIPI D-PHY transceivers at 10 Gbps per PHY
  • Up to 37 programmable source synchronous I/O pairs for camera and display interfacing
  • From 4 mm x 4 mm WLCS package (0.4 mm pitch) to 17 mm x 17 mm BGA package (0.8 mm pitch)
  • Lowest soft error rate in its class, 100X more reliable than competition

Jump to

Family Table

CrossLink-NX Device Selection Guide
Features LIFCL-17 LIFCL-40
Logic Cells 17K 39K
Embedded Memory (EBR) Bits (Kb) 432 1512
Large Memory (LRAM) Bits (Kb) 2560 1024
18 X 18 Multipliers 24 56
ADC Blocks 2 2
GPLL 2 3
Hardened 10 Gbps D-PHY Quads 2 2
Hardened 2.5 Gbps D-PHY Data Lanes (total) 8 8
5 Gb/s PCIe Gen2 Hard IP 1
0.4 mm Total I/O (Wide Range, High Performance) (D-PHY, PCIe)

LIFCL-17 LIFCL-40
72 wlcsp (3.7 x 4.1 mm) 36 (16, 20) (2, 0)
0.5 mm Total I/O (Wide Range, High Performance) (D-PHY, PCIe)

LIFCL-17 LIFCL-40
72 QFN (10 x 10 mm) 40 (18, 22) (1, 0) 40 (18, 22) (1, 0)
121 csfBGA (6 x 6 mm) 48 (24, 48) (2, 0) 72 (24, 48) (2, 0)
289 csBGA (9.5 x 9.5 mm) 180 (106, 74) (2, 1)
0.8 mm Total I/O (Wide Range, High Performance) (D-PHY, PCIe)

LIFCL-17 LIFCL-40
256 caBGA (14 x 14 mm) 72 (24, 48) (2, 0) 152 (78, 74) (2, 1)
400 caBGA (17 x 17 mm) 192 (118, 74) (2, 1)

Example Solutions

Edge AI Processing

  • Bridge one or multiple CSI-2 image sensors to processor interface (PCIe, CMOS, CSI-2)
  • Up to 3 Mb of internal RAM for processing
  • Offloads inferencing from CPU for object detection / counting
  • Combine video bridging and edge AI into a single device

Sensor Aggregation

  • Aggregate up to 13 MIPI CSI-2 image sensors into one MIPI CSI-2 output
  • Stitch data together into larger horizontal video frame
  • Use external DDR memory to stitch data into larger vertical video frame
  • Arbitrate data from image sensors using unique virtual channel numbers
  • Extend limited processor sensor interface capability and connect more sensors

Image Sensor Processing

  • Bridge one or multiple CSI-2 image sensors to processor interface (PCIe, CMOS, CSI-2)
  • Integrate full functional universal video pipeline
  • Examples: Debayer, color correction matrix, RGB gain, gamma correction…
  • Offloads ISP functionality from the processor

Signal Split or Duplication

  • Split or duplicate input CSI-2/DSI signal to multiple video outputs (up to 14)
  • Provide redundancy to sensor data in safety critical applications
  • Simplify applications which require one input to many display outputs

Videos

CrossLink-NXExpand Image

Introducing CrossLink-NX

CrossLink-NX FPGA is the first family of FPGAs implemented on the new Lattice Nexus Platform. CrossLink-NX provides the energy efficiency, small form factor, high reliability and higher performance developers need to enable innovative embedded vision solutions for the Edge.
CrossLink-NX: Power Efficiency DemoExpand Image

CrossLink-NX: Power Efficiency Demo

This demonstration measures the power consumption of Lattice’s CrossLink-NX FPGAs relative to other similar FPGAs using commercially available boards.
CrossLink-NX: Instant On DemoExpand Image

CrossLink-NX: Instant On Demo

This demonstration measures the IO wakeup time of Lattice’s CrossLink-NX FPGAs relative to other similar FPGAs using commercially available development boards.

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX Analog to Digital Converter Usage Guide
FPGA-TN-02129 1.0 12/10/2019 PDF 1.3 MB
CrossLink-NX Hardened D-PHY Usage Guide
FPGA-TN-02081 1.0 12/10/2019 PDF 1.2 MB
CrossLink-NX Hardware Checklist
FPGA-TN-02149 1.0 1/27/2020 PDF 1 MB
CrossLink-NX High-Speed I/O Interface
FPGA-TN-02097 1.0 12/10/2019 PDF 4.5 MB
CrossLink-NX I2C Hardened IP Usage Guide Application Note
FPGA-TN-02142 1.0 1/27/2020 PDF 1.4 MB
CrossLink-NX Memory Usage Guide
FPGA-TN-02094 1.0 12/10/2019 PDF 3.7 MB
CrossLink-NX Single Event Upset (SEU) Report
FPGA-TN-02174 1.0 1/28/2020 PDF 760.8 KB
CrossLink-NX sysClock PLL/DLL Design and Usage Guide
FPGA-TN-02095 1.0 12/10/2019 PDF 1.8 MB
CrossLink-NX sysCONFIG Usage Guide
FPGA-TN-02099 1.0 12/10/2019 PDF 2.1 MB
CrossLink-NX sysDSP Usage Guide
FPGA-TN-02096 1.0 12/10/2019 PDF 1.7 MB
CrossLink-NX sysI/O Usage Guide
FPGA-TN-02067 1.0 12/10/2019 PDF 985.3 KB
Power Management and Calculation for CrossLink-NX Devices
FPGA-TN-02075 1.0 12/10/2019 PDF 1.1 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 1.7 12/10/2019 PDF 1021.4 KB
Thermal Management
FPGA-TN-02044 3.5 12/10/2019 PDF 1.2 MB
Using TraceID
FPGA-TN-02084 1.9 12/10/2019 PDF 882.7 KB
CrossLink-NX Family Data Sheet
FPGA-DS-02049 0.8 12/11/2019 PDF 2.9 MB
CrossLink-NX LIFCL-40 Pinout
1.0 12/11/2019 CSV 30.8 KB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.1 2/28/2018 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX Family Data Sheet
FPGA-DS-02049 0.8 12/11/2019 PDF 2.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX Analog to Digital Converter Usage Guide
FPGA-TN-02129 1.0 12/10/2019 PDF 1.3 MB
CrossLink-NX Hardened D-PHY Usage Guide
FPGA-TN-02081 1.0 12/10/2019 PDF 1.2 MB
CrossLink-NX Hardware Checklist
FPGA-TN-02149 1.0 1/27/2020 PDF 1 MB
CrossLink-NX High-Speed I/O Interface
FPGA-TN-02097 1.0 12/10/2019 PDF 4.5 MB
CrossLink-NX I2C Hardened IP Usage Guide Application Note
FPGA-TN-02142 1.0 1/27/2020 PDF 1.4 MB
CrossLink-NX Memory Usage Guide
FPGA-TN-02094 1.0 12/10/2019 PDF 3.7 MB
CrossLink-NX Single Event Upset (SEU) Report
FPGA-TN-02174 1.0 1/28/2020 PDF 760.8 KB
CrossLink-NX sysClock PLL/DLL Design and Usage Guide
FPGA-TN-02095 1.0 12/10/2019 PDF 1.8 MB
CrossLink-NX sysCONFIG Usage Guide
FPGA-TN-02099 1.0 12/10/2019 PDF 2.1 MB
CrossLink-NX sysDSP Usage Guide
FPGA-TN-02096 1.0 12/10/2019 PDF 1.7 MB
CrossLink-NX sysI/O Usage Guide
FPGA-TN-02067 1.0 12/10/2019 PDF 985.3 KB
Power Management and Calculation for CrossLink-NX Devices
FPGA-TN-02075 1.0 12/10/2019 PDF 1.1 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 1.7 12/10/2019 PDF 1021.4 KB
Thermal Management
FPGA-TN-02044 3.5 12/10/2019 PDF 1.2 MB
Using TraceID
FPGA-TN-02084 1.9 12/10/2019 PDF 882.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX LIFCL-40 Pinout
1.0 12/11/2019 CSV 30.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.1 2/28/2018 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX LIFCL-40 Schematic Symbol
1.0 12/11/2019 ZIP 11.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX Product Brochure
I0269 1.0 12/11/2019 PDF 433.5 KB
Product Selector Guide
I0211 25.0 10/23/2019 PDF 8.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Crosslink-NX: Embedded Vision Processing at the Edge
1.0 1/18/2020 PDF 523.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LIFCL-40
1.0 12/11/2019 ZIP 21.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
CrossLink-NX Device Family DELPHI Models
1.0 12/10/2019 ZIP 172.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] LIFCL-40
1.0 12/11/2019 ZIP 10.5 MB


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