/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.3.0.109 */
/* Module Version: 5.6 */
/* Mon Oct 06 16:16:17 2014 */

/* parameterized module instance */
pll_10bit_2lane __ (.CLKI( ), .RST( ), .CLKOP( ), .CLKOS( ), .LOCK( ));
