/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.3.0.109 */
/* Module Version: 5.7 */
/* C:\lscc\diamond\3.3_x64\ispfpga\bin\nt64\scuba.exe -w -n simulation_fifo_10bit_to_10bit -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 512 -width 10 -rwidth 10 -no_enable -pe 10 -pf 508  */
/* Wed Oct 08 16:05:43 2014 */


`timescale 1 ns / 1 ps
module simulation_fifo_10bit_to_10bit (Data, WrClock, RdClock, WrEn, 
    RdEn, Reset, RPReset, Q, Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
    input wire [9:0] Data;
    input wire WrClock;
    input wire RdClock;
    input wire WrEn;
    input wire RdEn;
    input wire Reset;
    input wire RPReset;
    output wire [9:0] Q;
    output wire Empty;
    output wire Full;
    output wire AlmostEmpty;
    output wire AlmostFull;

    wire scuba_vhi;
    wire Empty_int;
    wire Full_int;
    wire scuba_vlo;

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam simulation_fifo_10bit_to_10bit_0_0.FULLPOINTER1 = "0b01111111110000" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.FULLPOINTER = "0b10000000000000" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.AFPOINTER1 = "0b01111110110000" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.AFPOINTER = "0b01111111000000" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.AEPOINTER1 = "0b00000010110000" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.AEPOINTER = "0b00000010100000" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.ASYNC_RESET_RELEASE = "SYNC" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.GSR = "DISABLED" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.RESETMODE = "ASYNC" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.REGMODE = "NOREG" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.CSDECODE_R = "0b11" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.CSDECODE_W = "0b11" ;
    defparam simulation_fifo_10bit_to_10bit_0_0.DATA_WIDTH_R = 18 ;
    defparam simulation_fifo_10bit_to_10bit_0_0.DATA_WIDTH_W = 18 ;
    FIFO8KB simulation_fifo_10bit_to_10bit_0_0 (.DI0(Data[0]), .DI1(Data[1]), 
        .DI2(Data[2]), .DI3(Data[3]), .DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]), 
        .DI7(Data[7]), .DI8(Data[8]), .DI9(Data[9]), .DI10(scuba_vlo), .DI11(scuba_vlo), 
        .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), .DI15(scuba_vlo), 
        .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), .CSW1(scuba_vhi), 
        .CSR0(scuba_vhi), .CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), 
        .WE(WrEn), .RE(RdEn), .ORE(RdEn), .CLKW(WrClock), .CLKR(RdClock), 
        .RST(Reset), .RPRST(RPReset), .DO0(Q[9]), .DO1(), .DO2(), .DO3(), 
        .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), .DO9(Q[0]), .DO10(Q[1]), 
        .DO11(Q[2]), .DO12(Q[3]), .DO13(Q[4]), .DO14(Q[5]), .DO15(Q[6]), 
        .DO16(Q[7]), .DO17(Q[8]), .EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull), 
        .FF(Full_int));

    assign Empty = Empty_int;
    assign Full = Full_int;


    // exemplar begin
    // exemplar end

endmodule
