/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.3.0.109 */
/* Module Version: 5.7 */
/* C:\lscc\diamond\3.3_x64\ispfpga\bin\nt64\scuba.exe -w -n LP_crossclk_cnvrt -lang verilog -synth synplify -bus_exp 7 -bb -arch xo3c00a -type ebfifo -depth 512 -width 32 -rwidth 32 -no_enable -pe 10 -pf 508  */
/* Mon Oct 06 16:16:25 2014 */


`timescale 1 ns / 1 ps
module LP_crossclk_cnvrt (Data, WrClock, RdClock, WrEn, RdEn, Reset, 
    RPReset, Q, Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
    input wire [31:0] Data;
    input wire WrClock;
    input wire RdClock;
    input wire WrEn;
    input wire RdEn;
    input wire Reset;
    input wire RPReset;
    output wire [31:0] Q;
    output wire Empty;
    output wire Full;
    output wire AlmostEmpty;
    output wire AlmostFull;

    wire scuba_vhi;
    wire Empty_int;
    wire Full_int;
    wire scuba_vlo;

    defparam LP_crossclk_cnvrt_0_1.FULLPOINTER1 = "0b01111111110000" ;
    defparam LP_crossclk_cnvrt_0_1.FULLPOINTER = "0b10000000000000" ;
    defparam LP_crossclk_cnvrt_0_1.AFPOINTER1 = "0b01111110110000" ;
    defparam LP_crossclk_cnvrt_0_1.AFPOINTER = "0b01111111000000" ;
    defparam LP_crossclk_cnvrt_0_1.AEPOINTER1 = "0b00000010110000" ;
    defparam LP_crossclk_cnvrt_0_1.AEPOINTER = "0b00000010100000" ;
    defparam LP_crossclk_cnvrt_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
    defparam LP_crossclk_cnvrt_0_1.GSR = "DISABLED" ;
    defparam LP_crossclk_cnvrt_0_1.RESETMODE = "ASYNC" ;
    defparam LP_crossclk_cnvrt_0_1.REGMODE = "NOREG" ;
    defparam LP_crossclk_cnvrt_0_1.CSDECODE_R = "0b11" ;
    defparam LP_crossclk_cnvrt_0_1.CSDECODE_W = "0b11" ;
    defparam LP_crossclk_cnvrt_0_1.DATA_WIDTH_R = 18 ;
    defparam LP_crossclk_cnvrt_0_1.DATA_WIDTH_W = 18 ;
    FIFO8KB LP_crossclk_cnvrt_0_1 (.DI0(Data[0]), .DI1(Data[1]), .DI2(Data[2]), 
        .DI3(Data[3]), .DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]), .DI7(Data[7]), 
        .DI8(Data[8]), .DI9(Data[9]), .DI10(Data[10]), .DI11(Data[11]), 
        .DI12(Data[12]), .DI13(Data[13]), .DI14(Data[14]), .DI15(Data[15]), 
        .DI16(Data[16]), .DI17(Data[17]), .CSW0(scuba_vhi), .CSW1(scuba_vhi), 
        .CSR0(scuba_vhi), .CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), 
        .WE(WrEn), .RE(RdEn), .ORE(RdEn), .CLKW(WrClock), .CLKR(RdClock), 
        .RST(Reset), .RPRST(RPReset), .DO0(Q[9]), .DO1(Q[10]), .DO2(Q[11]), 
        .DO3(Q[12]), .DO4(Q[13]), .DO5(Q[14]), .DO6(Q[15]), .DO7(Q[16]), 
        .DO8(Q[17]), .DO9(Q[0]), .DO10(Q[1]), .DO11(Q[2]), .DO12(Q[3]), 
        .DO13(Q[4]), .DO14(Q[5]), .DO15(Q[6]), .DO16(Q[7]), .DO17(Q[8]), 
        .EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int));

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam LP_crossclk_cnvrt_1_0.FULLPOINTER1 = "0b00000000000000" ;
    defparam LP_crossclk_cnvrt_1_0.FULLPOINTER = "0b11111111110000" ;
    defparam LP_crossclk_cnvrt_1_0.AFPOINTER1 = "0b00000000000000" ;
    defparam LP_crossclk_cnvrt_1_0.AFPOINTER = "0b11111111110000" ;
    defparam LP_crossclk_cnvrt_1_0.AEPOINTER1 = "0b00000000000000" ;
    defparam LP_crossclk_cnvrt_1_0.AEPOINTER = "0b11111111110000" ;
    defparam LP_crossclk_cnvrt_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
    defparam LP_crossclk_cnvrt_1_0.GSR = "DISABLED" ;
    defparam LP_crossclk_cnvrt_1_0.RESETMODE = "ASYNC" ;
    defparam LP_crossclk_cnvrt_1_0.REGMODE = "NOREG" ;
    defparam LP_crossclk_cnvrt_1_0.CSDECODE_R = "0b11" ;
    defparam LP_crossclk_cnvrt_1_0.CSDECODE_W = "0b11" ;
    defparam LP_crossclk_cnvrt_1_0.DATA_WIDTH_R = 18 ;
    defparam LP_crossclk_cnvrt_1_0.DATA_WIDTH_W = 18 ;
    FIFO8KB LP_crossclk_cnvrt_1_0 (.DI0(Data[18]), .DI1(Data[19]), .DI2(Data[20]), 
        .DI3(Data[21]), .DI4(Data[22]), .DI5(Data[23]), .DI6(Data[24]), 
        .DI7(Data[25]), .DI8(Data[26]), .DI9(Data[27]), .DI10(Data[28]), 
        .DI11(Data[29]), .DI12(Data[30]), .DI13(Data[31]), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(scuba_vhi), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(RdEn), .ORE(RdEn), .CLKW(WrClock), 
        .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[27]), .DO1(Q[28]), 
        .DO2(Q[29]), .DO3(Q[30]), .DO4(Q[31]), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(Q[18]), .DO10(Q[19]), .DO11(Q[20]), .DO12(Q[21]), .DO13(Q[22]), 
        .DO14(Q[23]), .DO15(Q[24]), .DO16(Q[25]), .DO17(Q[26]), .EF(), .AEF(), 
        .AFF(), .FF());

    assign Empty = Empty_int;
    assign Full = Full_int;


    // exemplar begin
    // exemplar end

endmodule
