/* Verilog netlist generated by SCUBA Diamond_3.1_Production (93) */
/* Module Version: 5.5 */
/* C:\lscc\diamond\3.1_x64\ispfpga\bin\nt64\scuba.exe -w -n deser -lang verilog -synth synplify -bus_exp 7 -bb -arch xo3c00a -type iol -mode in -io_type LVDS25 -width 4 -freq_in 222.75 -gear 4 -clk eclk -del 32  */
/* Mon Feb 24 20:09:15 2014 */


`timescale 1 ns / 1 ps
module deser (alignwd, clk, clk_s, init, reset, rx_ready, sclk, datain, 
    q)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute deser dont_touch true 
    input wire alignwd;
    input wire clk;
    input wire clk_s;
    input wire init;
    input wire reset;
    input wire [3:0] datain;
    output wire rx_ready;
    output wire sclk;
    output wire [31:0] q;

    wire scuba_vlo;
    wire opensync_0;
    wire opensync_1;
    wire opensync_cken;
    wire opensync_2;
    wire q7_3;
    wire q6_3;
    wire q5_3;
    wire q4_3;
    wire q3_3;
    wire q2_3;
    wire q1_3;
    wire q0_3;
    wire q7_2;
    wire q6_2;
    wire q5_2;
    wire q4_2;
    wire q3_2;
    wire q2_2;
    wire q1_2;
    wire q0_2;
    wire q7_1;
    wire q6_1;
    wire q5_1;
    wire q4_1;
    wire q3_1;
    wire q2_1;
    wire q1_1;
    wire q0_1;
    wire q7_0;
    wire q6_0;
    wire q5_0;
    wire q4_0;
    wire q3_0;
    wire q2_0;
    wire q1_0;
    wire q0_0;
    wire sclk_t;
    wire cdiv1;
    wire eclko;
    wire xstop;
    wire xstart;
    wire opensync_3;
    wire eclki;
    wire lock_chk;
    wire scuba_vhi;
    wire dataini_t3;
    wire dataini_t2;
    wire dataini_t1;
    wire dataini_t0;
    wire buf_clk;
    wire buf_dataini3;
    wire buf_dataini2;
    wire buf_dataini1;
    wire buf_dataini0;

    defparam LUT4_1.initval =  16'h0a78 ;
    ROM16X1A LUT4_1 (.AD3(opensync_0), .AD2(opensync_3), .AD1(lock_chk), 
        .AD0(init), .DO0(opensync_cken));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam LUT4_0.initval =  16'hfffe ;
    ROM16X1A LUT4_0 (.AD3(opensync_0), .AD2(opensync_1), .AD1(scuba_vlo), 
        .AD0(scuba_vlo), .DO0(xstop));

    FD1P3BX FF_3 (.D(opensync_3), .SP(opensync_cken), .CK(clk_s), .PD(reset), 
        .Q(opensync_0))
             /* synthesis GSR="ENABLED" */;

    FD1P3DX FF_2 (.D(opensync_0), .SP(opensync_cken), .CK(clk_s), .CD(reset), 
        .Q(opensync_1))
             /* synthesis GSR="ENABLED" */;

    FD1P3DX FF_1 (.D(opensync_1), .SP(opensync_cken), .CK(clk_s), .CD(reset), 
        .Q(opensync_2))
             /* synthesis GSR="ENABLED" */;

    FD1P3DX FF_0 (.D(opensync_2), .SP(opensync_cken), .CK(clk_s), .CD(reset), 
        .Q(opensync_3))
             /* synthesis GSR="ENABLED" */;

    IDDRX4B Inst4_IDDRX4B3 (.D(dataini_t3), .ECLK(eclko), .SCLK(sclk_t), 
        .RST(reset), .ALIGNWD(alignwd), .Q0(q0_3), .Q1(q1_3), .Q2(q2_3), 
        .Q3(q3_3), .Q4(q4_3), .Q5(q5_3), .Q6(q6_3), .Q7(q7_3));

    IDDRX4B Inst4_IDDRX4B2 (.D(dataini_t2), .ECLK(eclko), .SCLK(sclk_t), 
        .RST(reset), .ALIGNWD(alignwd), .Q0(q0_2), .Q1(q1_2), .Q2(q2_2), 
        .Q3(q3_2), .Q4(q4_2), .Q5(q5_2), .Q6(q6_2), .Q7(q7_2));

    IDDRX4B Inst4_IDDRX4B1 (.D(dataini_t1), .ECLK(eclko), .SCLK(sclk_t), 
        .RST(reset), .ALIGNWD(alignwd), .Q0(q0_1), .Q1(q1_1), .Q2(q2_1), 
        .Q3(q3_1), .Q4(q4_1), .Q5(q5_1), .Q6(q6_1), .Q7(q7_1));

    IDDRX4B Inst4_IDDRX4B0 (.D(dataini_t0), .ECLK(eclko), .SCLK(sclk_t), 
        .RST(reset), .ALIGNWD(alignwd), .Q0(q0_0), .Q1(q1_0), .Q2(q2_0), 
        .Q3(q3_0), .Q4(q4_0), .Q5(q5_0), .Q6(q6_0), .Q7(q7_0));

    defparam Inst3_CLKDIVC.DIV = "4.0" ;
    CLKDIVC Inst3_CLKDIVC (.RST(reset), .CLKI(eclko), .ALIGNWD(alignwd), 
        .CDIV1(cdiv1), .CDIVX(sclk_t));

    ECLKSYNCA Inst2_ECLKSYNCA (.ECLKI(eclki), .STOP(xstop), .ECLKO(eclko));

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    defparam udel_dataini3.DEL_VALUE = "DELAY0" ;
    defparam udel_dataini3.DEL_MODE = "ECLK_CENTERED" ;
    DELAYE udel_dataini3 (.A(buf_dataini3), .Z(dataini_t3));

    defparam udel_dataini2.DEL_VALUE = "DELAY0" ;
    defparam udel_dataini2.DEL_MODE = "ECLK_CENTERED" ;
    DELAYE udel_dataini2 (.A(buf_dataini2), .Z(dataini_t2));

    defparam udel_dataini1.DEL_VALUE = "DELAY0" ;
    defparam udel_dataini1.DEL_MODE = "ECLK_CENTERED" ;
    DELAYE udel_dataini1 (.A(buf_dataini1), .Z(dataini_t1));

    defparam udel_dataini0.DEL_VALUE = "DELAY0" ;
    defparam udel_dataini0.DEL_MODE = "ECLK_CENTERED" ;
    DELAYE udel_dataini0 (.A(buf_dataini0), .Z(dataini_t0));

    IB Inst1_IB3 (.I(datain[3]), .O(buf_dataini3))
             /* synthesis IO_TYPE="LVDS25" */;

    IB Inst1_IB2 (.I(datain[2]), .O(buf_dataini2))
             /* synthesis IO_TYPE="LVDS25" */;

    IB Inst1_IB1 (.I(datain[1]), .O(buf_dataini1))
             /* synthesis IO_TYPE="LVDS25" */;

    IB Inst1_IB0 (.I(datain[0]), .O(buf_dataini0))
             /* synthesis IO_TYPE="LVDS25" */;

    assign sclk = sclk_t;
    assign q[31] = q7_3;
    assign q[30] = q7_2;
    assign q[29] = q7_1;
    assign q[28] = q7_0;
    assign q[27] = q6_3;
    assign q[26] = q6_2;
    assign q[25] = q6_1;
    assign q[24] = q6_0;
    assign q[23] = q5_3;
    assign q[22] = q5_2;
    assign q[21] = q5_1;
    assign q[20] = q5_0;
    assign q[19] = q4_3;
    assign q[18] = q4_2;
    assign q[17] = q4_1;
    assign q[16] = q4_0;
    assign q[15] = q3_3;
    assign q[14] = q3_2;
    assign q[13] = q3_1;
    assign q[12] = q3_0;
    assign q[11] = q2_3;
    assign q[10] = q2_2;
    assign q[9] = q2_1;
    assign q[8] = q2_0;
    assign q[7] = q1_3;
    assign q[6] = q1_2;
    assign q[5] = q1_1;
    assign q[4] = q1_0;
    assign q[3] = q0_3;
    assign q[2] = q0_2;
    assign q[1] = q0_1;
    assign q[0] = q0_0;
    assign rx_ready = xstart;
    assign xstart = opensync_3;
    assign eclki = buf_clk;
    assign lock_chk = scuba_vhi;
    assign buf_clk = clk;


    // exemplar begin
    // exemplar attribute FF_3 GSR ENABLED
    // exemplar attribute FF_2 GSR ENABLED
    // exemplar attribute FF_1 GSR ENABLED
    // exemplar attribute FF_0 GSR ENABLED
    // exemplar attribute Inst1_IB3 IO_TYPE LVDS25
    // exemplar attribute Inst1_IB2 IO_TYPE LVDS25
    // exemplar attribute Inst1_IB1 IO_TYPE LVDS25
    // exemplar attribute Inst1_IB0 IO_TYPE LVDS25
    // exemplar end

endmodule
