lappend auto_path "C:/lscc/diamond/3.3_x64/data/script"
package require simulation_generation
set ::bali::simulation::Para(PROJECT) {rtl_verilog}
set ::bali::simulation::Para(PROJECTPATH) {C:/Users/rjohn/Desktop/check_before_qa/rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/simulation/ecp5/verilog}
set ::bali::simulation::Para(FILELIST) {"C:/Users/rjohn/Desktop/check_before_qa/rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/simulation/ecp5/MIPI_CSI2_Serial2Parallel_Bridge_tb_10bit.vo" "C:/Users/rjohn/Desktop/check_before_qa/rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/testbench/verilog/simulation_fifo_10bit_to_10bit.v" "C:/Users/rjohn/Desktop/check_before_qa/rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/testbench/verilog/MIPI_CSI2_Serial2Parallel_Bridge_tb_10bit_4lane_ecp5.v" }
set ::bali::simulation::Para(GLBINCLIST) {}
set ::bali::simulation::Para(INCLIST) {"none" "none" "none"}
set ::bali::simulation::Para(WORKLIBLIST) {"" "" "" }
set ::bali::simulation::Para(COMPLIST) {"none" "none" "none" }
set ::bali::simulation::Para(SIMLIBLIST) {pmi_work ovi_ecp5u}
set ::bali::simulation::Para(MACROLIST) {}
set ::bali::simulation::Para(SIMULATIONTOPMODULE) {mipi_csi2_tb}
set ::bali::simulation::Para(SIMULATIONINSTANCE) {}
set ::bali::simulation::Para(LANGUAGE) {VERILOG}
set ::bali::simulation::Para(SDFPATH)  {}
set ::bali::simulation::Para(ADDTOPLEVELSIGNALSTOWAVEFORM)  {1}
set ::bali::simulation::Para(RUNSIMULATION)  {1}
set ::bali::simulation::Para(HDLPARAMETERS) {}
set ::bali::simulation::Para(POJO2LIBREFRESH)    {}
set ::bali::simulation::Para(POJO2MODELSIMLIB)   {}
::bali::simulation::ActiveHDL_Run
