/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.3.0.109 */
/* Module Version: 5.7 */
/* Wed Oct 08 16:05:43 2014 */

/* parameterized module instance */
simulation_fifo_10bit_to_10bit __ (.Data( ), .WrClock( ), .RdClock( ), 
    .WrEn( ), .RdEn( ), .Reset( ), .RPReset( ), .Q( ), .Empty( ), 
    .Full( ), .AlmostEmpty( ), .AlmostFull( ));
