/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.3.0.109 */
/* Module Version: 5.7 */
/* Mon Oct 06 16:16:25 2014 */

/* parameterized module instance */
LP_crossclk_cnvrt __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), 
    .RdEn( ), .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ), 
    .AlmostEmpty( ), .AlmostFull( ));
