/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.3.0.109 */
/* Module Version: 5.7 */
/* Mon Oct 06 16:16:32 2014 */

/* parameterized module instance */
deser __ (.alignwd( ), .clk( ), .clk_s( ), .init( ), .reset( ), 
    .rx_ready( ), .sclk( ), .datain( ), .q( ));
