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NOTE: By default the Synthesis tool is LSE but design is also synthesized in Synplify Pro
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-------------------------------------------------------------------------
 CSI2 XO2 Sensor Bridge Design Readme
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About Design:
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The Mobile Industry Processor Interface (MIPI) has become a specification standard for interfacing components in
consumer mobile devices. The MIPI camera Serial Interface (CSI2) specification provides a protocol layer interface
definition, which is used to interface with camera. Normally an applications processor (AP) would directly connect
to a camera that has a CSI2 interface.

The Lattice Parallel to MIPI CSI2 Tx Bridge Reference Design allows a traditional processor to connect to a CSI2 camera.
The Parallel to MIPI CSI2 TX Bridge Reference Design allows users to deliver data to a MIPI CSI2 compatible camera from a standard parallel
video interface.

The Parallel to MIPI CSI2 TX Bridge Reference Design converts a standard parallel video interface into DSI byte
packets. The input interface for the design consists of a data bus (PIXDATA), vertical and horizontal sync flags
(VSYNC and HSYNC), a data enable and a clock (DE and PIXCLK). The parallel video interface consists of RGB
or YCbCr data. This parallel bus is converted to the appropriate CSI2 output format. The CSI2 output serializes HS
(High Speed) data and controls LP (Low Power) data and transfers them.


File Structure:
---------------

1. rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/docs/rd1146.pdf                                                                    --> Design document
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/docs/rd1146_readme.txt                                                             --> This document
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/docs/revision_history.xlsx                                                         --> Revision History
   
2. rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/projects/<Device_name>/<verilog>/*.ldf                                             --> Lattice Diamond Design files to open diamond project
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/projects/<Device_name>/<verilog>/*.lpf                                             --> Preference constraint file for Diamond
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/projects/<Device_name>/<verilog>/*.sty                                             -->Lattice Diamond Startegy file
   
  
3. rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/simulation/<Device_name>/<verilog>/rtl_verilog.do                                   --> RTL simulation script file
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/simulation/<Device_name>/<verilog>/timing_verilog.do                                --> Timing simulation script file
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/simulation/<Device_name>/MIPI_CSI2_Serial2Parallel_Bridge_tb_10bit.vo               --> Verilog Simulation model
   

4. rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><ecp5>/deser.v                                                       --> Verilog File for ecp5
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><ecp5>/gearing_converter_fifo.v                                      --> Verilog File for ecp5
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><ecp5>/lp_crossclk_cnvrt.v                                           --> Verilog File for ecp5
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><ecp5>/mipi_csi2_serial2parallel_bridge.v                            --> Verilog File for ecp5
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><ecp5>/mipi_csi2_serial2parallel_bridge_demo.v                       --> Verilog File for ecp5
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><ecp5>/pll_10bit_4lane.v                                             --> Verilog File for ecp5
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><ecp5>/pll_10bit_4lane_lp.v                                          --> Verilog File for ecp5
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog>/<mipi_csi2_serial2parallel_bb.v                                     --> Verilog File for all
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog>/<mipi_csi2_serial2parallel_bridge.v                                 --> Verilog File for xo2 and xo3l
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog>/<mipi_csi2_serial2parallel_bridge.v                                 --> Verilog File for xo2 and xo3l
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><Device_name>/<ngo>/MIPI_CSI2_Serial2Parallel_10s_2s_RAW10.ngo       --> ngo File for synplify pro 
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><Device_name>/<ngo>/MIPI_CSI2_Serial2Parallel.ngo                    --> ngo File for LSE 
   rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/source/<verilog><Device_name>/ipexpress                                              --> IPExpress Folder for xo2 and xo3l
   
   
5.  rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/testbench/<verilog>/MIPI_CSI2_Serial2Parallel_Bridge_tb_10bit_4lane_ecp5.v           --> Verilog File for xo2 and xo3l
    rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/testbench/<verilog>/mipi_csi2_serial2parallel_bridge_tb.v                            --> Verilog File for ecp5
    rd1146_mipi_csi2_to_cmos_parallel_sensor_bridge/rd1146/testbench/<verilog>/simulation_fifo_10bit_to_10bit_ecp5.v                            --> Verilog File for ecp5
	

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HOW TO OPEN A PROJECT IN DIAMOND:
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1. Unzip the respective design files.
2. Launch Diamond and select "File -> Open -> Project..."
3. In the Open Project dialog, enter the Project location -- "\rd1146\project",select one device and then select one project.
4. Click Finish. Now the project is successfully loaded. 

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HOW TO RUN PLACE AND ROUTE, JEDEC GENERATION, AND TIMING ANALYSIS IN DIAMOND:
---------------------------------------------------------------------------------------------------------------

1. Click the Process tab in the process panel of the Diamond dashboard. 
   Double click on Place and Route Design. This will bring the
   design through synthesis, mapping, and place and route.
2. Click the Process tab in the process panel of the Diamond dashboard.
   a) MachXO2 ,MachXO3L and LatticeECP5 : Double click on "Export Files -> JEDEC File". This will generate
      the Jedec file for the design.
3. Once Place and Route is done, user can double click on Place and Route Trace
   Report on the right-side panel to get the timing analysis result.
4. Double click on "Export Files -> verilog Simulation File". This will generate
   the VO and SDF files for the timing simulation of the design.
 
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HOW TO RUN SIMULATION FROM DIAMOND:
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There are two ways to bring up the Simulation:
A. The simulation environment can be accessed by Lattice Diamond Simulation Wizard file: 
    1. double clicking on the "XXXXXX.spf" file in Lattice Diamond 
	2. Press SkiptoEnd button
	3. Click Finish.  This will bring up the Aldec simulator automatically.
	4. Add the required signals into the Waveform panel 
	5. Run 100ns.
    6. The simulation should end without error and  a script similar to this 
   will be in the Console panel for functional simulation:
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3d6
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3d7
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3d8
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3d9
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3da
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3db
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3dc
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3dd
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3de
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3df
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e0
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e1
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e2
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e3
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e4
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e5
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e6
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e7
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e8
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3e9
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3ea
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3eb
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3ec
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3ed
# KERNEL: OUTPUT DATA MATCHES WITH THE EXPECTED DATA AS 3ee
# KERNEL: stopped at time: 100 us
   7. if you find find the following in the console panel:
# KERNEL: XXXXXXXXXXX DATA MISMATCH XXXXXXXXXXX
# RUNTIME: Info: RUNTIME_XXXX MIPI_CSI2_Serial2Parallel_Bridge_tb_self_checking.v (264): $finish called.

then it indicates that there are some errors in the simulation

(or)

B. Starting the simulation from the Simulation Wizard in Diamond:
  1. Bring up the Simulation Wizard under the Tools menu 
  2. Next provide a name for simulation project, and select RTL simulation
  3. Add the respective testbench file to the source file list.
  4. Click Finish.  This will bring up the Aldec simulator automatically.
  5. In Aldec environment, you can manually activate the simulation or you can use a script
	5.1 Use the provided script in the rd1146\simulation\<language> directory
	    a. For functional simulation, change the PROJ_DIR to your local directory Address of the "simulation"
	  
		b. For POST-ROUTE simulation, open the script and change the following:
		   i) change the PROJ_DIR to your local directory Address of the "simulation"
		  ii) open the "MIPI_CSI2_Serial2Parallel_Bridge_tb_xo3l.v" file and uncomment the "`define tim_sim" statement.
		c. Click Tools > Execute Macro and select the xxx.do file to run the simulation
		d. This will run the simulation until 100us
    5.2 You can manually activate the simulation		
		a. Click Simulation > Initialize Simulation
		   If prompted to select a top-level file, select the testbench as the top-level file and click Ok.
		b. Click File > New > Waveform, this will bring up the Waveform panel
		c. Click on the top-level testbench, drag all the signals into the Waveform panel
		d. Click Simulation > Run 100us.
  6. The simulation should end without error and  a script similar to that described above 
   will be in the Console panel for functional simulation:


  7. if you find find the following in the console panel:
       # KERNEL: XXXXXXXXXXX DATA MISMATCH XXXXXXXXXXX
       # RUNTIME: Info: RUNTIME_XXXX MIPI_CSI2_Serial2Parallel_Bridge_tb_self_checking.v (264): $finish called.
    then it indicates that there are some errors in the simulation
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